T8.3 | A High-Performance Heterogeneous 2T0C DRAM with PSLC-Si/IGZO Complementary Gain Cell for Monolithic 3D Leveraging Capacitive Coupling

This study experimentally demonstrates a high-performance monolithic 3D (M3D) integrated 2-transistor-0-capacitor (2T0C) DRAM cell utilizing a complementary gain cell (CGC) with n-IGZO and p-channel PSLC-Si. Using patterned seedless laser crystallization (PSLC), we achieved a world-record grain size of 32.3 μm and a hole mobility of 265 cm²/Vs for the read-transistor (R-Tr). The CGC architecture leverages capacitive coupling (C.C.) to boost the sensing margin (SM) to ~10⁶, satisfying the 1k-array criterion (SM > 10⁴) and outperforming conventional 2-nIGZO 2T0C. Simulation confirms an estimated read time of 11.8 ns. These findings establish the M3D CGC 2T0C DRAM as a candidate for high-density, and high-performance 3D memory solutions that overcome the limitations of conventional architecture.