T8 | DRAM

Type

Technology Technical Session

Speakers

Session Chair

SVP at Rambus

Session Chair

Professor at National Taiwan University

Presentations

Wed. Jun. 17 | 3:25 PM - 3:50 PM – T8.1 | 3D Orthogonal Die Stacking Technology for DRAM-on-GPU Integration Using Contactless Die-to-Die Interface (BSPA Nominee)

Wed. Jun. 17 | 3:50 PM - 4:15 PM – T8.2 | Highly stackable 3D DRAM of Dual-gate IGZO 2T0C with Record 3 bits/cell and 400s Data Retention

Wed. Jun. 17 | 4:15 PM - 4:40 PM – T8.3 | A High-Performance Heterogeneous 2T0C DRAM with PSLC-Si/IGZO Complementary Gain Cell for Monolithic 3D Leveraging Capacitive Coupling

Wed. Jun. 17 | 4:40 PM - 5:05 PM – T8.4 | Vertical-Die (V-die) 3.5D Integration for Cool Ultrahigh-Bandwidth Memory Systems

Wed. Jun. 17 | 5:05 PM - 5:30 PM – T8.5 | Electrical Characteristics of the 4F2 Vertical Gate (VG) DRAM integrated with Bit-Line Shielding (BLS) and Back Gate (BG) Transistor (Late News)